MOSI Protocol (Modified, Owned, Shared, Invalid).MSI Protocol (Modified, Shared, Invalid).If the processor wants to modify the data block, it has to send a request to the owner of the same data block. Invalid (I): The cache has a data block that does not have valid data.Owned (O): The cache holds the data block and is the owner of that block.All processors have a valid copy of the data block in their caches. Shared (S): A data block in the main memory is shared by many processors.The processor is the exclusive owner of the data block. Exclusive (E): When the processor tries to modify a data block in its cache, it must invalidate the copy of the same data block in other caches.The processor modifying the data block is the owner of that data block. Modify (M): The data block in a cache is modified.To maintain the cache coherence, the cache controller maintains the state for every data block which helps in maintaining the coherence. The system returns the exact same data from the main memory if there are no caches. Cache coherence not only ensures the data consistency between the cache and the main memory, but also the data consistency between the caches of each CPU. Assuming a 1 level of the local cache only, in a multiprocessors system, the data in the cache line of each CPU is a copy of the data in the corresponding location in their shared memory. The memory instructions must be executed sequentially.Ĭache coherence is a microarchitectural feature that the programmer does not need to know about. The memory consistency is the data consistency between the cache and the main memory. In a single-core system, the data in the cache line is the corresponding location in the main memory. Memory consistency is an architectural feature that must be known by programmers. The data consistency or memory consistency is mainly discussed from the perspective of a single core. So, the current trend is to adopt hardware to maintain cache coherence. The method of maintaining cache coherence is not used now because of the higher cost of maintenance. There are 2 ways to maintain cache coherence, namely hardware, and software. How does the L1 cache between different CPUs ensure cache coherence? Cache coherence is to ensure that the changes in the values of shared operands (data) are propagated throughout the system. When one of the copies of data is changed, the other copies must reflect that change. In a shared-memory multiprocessor system, it is possible to have many copies of shared data: 1 copy in the main memory and 1 copy in the local cache of each processor. Assuming a 2-core system, there are 2 L1 caches. We all know that each processor has its own private L1 cache (not subdividing iCache and dCache). However, when Moore’s law is likely not applicable today, the manufacturers try to increase the number of CPU cores to improve the overall performance of the system. It is an empirical relationship linked to gains from experience in production. Moore’s law is the observation that the number of transistors in a dense integrated circuit (IC) doubles about every 2 years. Now, we discuss the cache coherence problems. After so many articles I wrote, you should have a clear understanding of cache.
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